1 /*********************************************************************
  2     FileName:           REN70V05.c
  3     Dependencies:       See #includes
  4     Processor:          PIC32MZ
  5     Hardware:           MainBrain MZ
  6     Complier:           XC32 4.40
  7     Author:             Larry Knight 2023
  8 /*********************************************************************
  9  
 10     Software License Agreement:
 11  
 12     Licensed under the Apache License, Version 2.0 (the "License");
 13     you may not use this file except in compliance with the License.
 14     You may obtain a copy of the License at
 15 
 16     http://www.apache.org/licenses/LICENSE-2.0
 17 
 18     Unless required by applicable law or agreed to in writing, software
 19     distributed under the License is distributed on an "AS IS" BASIS,
 20     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 21     See the License for the specific language governing permissions and
 22     limitations under the License.
 23  
 24     Description:
 25         System Clock = 200 - 250 MHz
 26 
 27     File Description:
 28 
 29     Change History:
 30  
 31 /***********************************************************************/
 32 
 33 /*     Flag Table        */
 34 //Flag 000 = address 0000 - 03ff
 35 //Flag 001 = address 0400 - 07ff
 36 //Flag 010 = address 0800 - 0bff
 37 //Flag 011 = address 0c00 - 0fff
 38 //Flag 100 = address 1000 - 13ff
 39 //Flag 101 = address 1400 - 17ff
 40 //Flag 110 = address 1800 - 1bff
 41 //Flag 110 = address 1c00 - 1fff
 42     
 43 
 44 #include <xc.h>
 45 #include "MainBrain.h"
 46 
 47 uint8_t mdata_70V05;
 48 uint32_t address_70V05;
 49 volatile bool SRAM_BUSY = false;
 50 
 51 void REN70V05_Init(void)
 52 {    
 53    //RA0 = /CS1
 54     ANSELA = 0;
 55     TRISAbits.TRISA0 = 0;
 56     PORTAbits.RA0 = 1;
 57     
 58     //RG15 = /SEM
 59     TRISGbits.TRISG15 = 0;
 60     PORTGbits.RG15 = 1;
 61     
 62     //INT1 - INTR
 63     TRISEbits.TRISE8 = 1;
 64     
 65     //RB5 = M/S
 66     TRISBbits.TRISB5 = 0;    
 67     PORTBbits.RB5 = 1;
 68     
 69     //BUSY - BUSYR
 70     ANSELE = 0;
 71     TRISEbits.TRISE9 = 1;
 72     
 73     CNCONEbits.ON = 1;
 74     
 75     // Enable CN interrupt on RE9
 76     CNENEbits.CNIEE9 = 1;
 77     
 78     // Configure CN interrupt
 79     // Enable CN interrupt
 80     IEC3bits.CNEIE = 1;    
 81     
 82     // Set priority
 83     IPC30bits.CNEIP = 5; 
 84     IPC30bits.CNEIS = 1;
 85     
 86     // Clear the interrupt flag 
 87      IFS3bits.CNEIF = 0;       
 88      
 89      REN70V05_WR(0,1);
 90      Delay32(1,10000);
 91      mdata_70V05 = 0;
 92      REN70V05_RD(0);
 93      if(mdata_70V05 != 1)
 94      {
 95          lastError = lastError | 4;
 96          return;
 97      }
 98      
 99     //Format the SRAM
100     for(int i=0;i<24;i++)
101     {
102         REN70V05_WR(0x400 + i, 0);
103     }
104     
105     for(int i=0;i<24;i++)
106     {
107         REN70V05_WR(0x800 + i, 0);
108     }
109 
110     for(int i=0;i<24;i++)
111     {
112         REN70V05_WR(0xc00 + i, 0);
113     }
114 
115     for(int i=0;i<24;i++)
116     {
117         REN70V05_WR(0x1000 + i, 0);
118     }
119 
120     for(int i=0;i<24;i++)
121     {
122         REN70V05_WR(0x1400 + i, 0);
123     }
124 
125     for(int i=0;i<24;i++)
126     {
127         REN70V05_WR(0x1800 + i, 0);
128     }
129 
130     for(int i=0;i<24;i++)
131     {
132         REN70V05_WR(0x1c00 + i, 0);
133     }
134 }
135 
136 int8_t REN70V05_RD(uint32_t address_70V05)
137 {        
138     SRAM_BUSY = false;
139     
140     //get data
141     PMRADDR = address_70V05;
142     
143     //CS1
144     PORTAbits.RA0 = 0;    
145 
146     //dummy read
147     while(PMMODEbits.BUSY == 1);
148     mdata_70V05 = PMRDIN;
149     
150     while(PMMODEbits.BUSY == 1);
151     mdata_70V05 = PMRDIN;
152 
153     //CS1
154     PORTAbits.RA0 = 1;    
155     
156     return mdata_70V05;
157 }
158 
159 void REN70V05_WR(uint32_t address_70V05, uint8_t mdata_70V05)
160 {        
161     PMWADDR = address_70V05;
162     
163     //CS1
164     PORTAbits.RA0 = 0; 
165     
166     while(PMMODEbits.BUSY == 1);
167     PMDOUT = mdata_70V05;
168     while(PMMODEbits.BUSY == 1);
169     
170     if(SRAM_BUSY == true)
171     {
172         while(PMMODEbits.BUSY == 1);
173         PMDOUT = mdata_70V05;
174         while(PMMODEbits.BUSY == 1);
175     }
176     
177     SRAM_BUSY = false;
178     
179     //CS1
180     PORTAbits.RA0 = 1;    
181 }
182 
183 void __attribute__((vector(_CHANGE_NOTICE_E_VECTOR), interrupt(ipl5srs), nomips16)) CN_ISR()
184 { 
185     // Check if the interrupt is caused by RE9 and that it was the falling edge
186     if (CNSTATEbits.CNSTATE9 && !PORTEbits.RE9)
187     {    
188         Delay32(0, 1);
189         SRAM_BUSY = true;
190     }
191     
192     // Clear the interrupt flag
193     IFS3bits.CNEIF = 0;
194 }