Sheet 1

1.0 3 of 8 1 09/05/2021

-10 0 400 0 0 0 0 Arial -21 9 400 0 0 0 0 Arial -11 5 400 0 0 0 0 Arial -19 8 400 0 0 0 0 Arial -11 5 400 0 0 0 0 Arial 000000 4 C0C0C0 4 C0C0C0 4 808080 4 000000 4 000000 1 000000 2 -1 000000 Output U? Output Tab 1 $$SPICE_PROLOG_PRIORITY 5 000002 0.00000,0.00000 $$SPICE_EPILOG_PRIORITY 5 000002 0.00000,0.00000 Package package name for PCB layout 000001 0.00000,0.00000 C C? Capacitor 1 $$SPICE_PROLOG_PRIORITY 5 000002 0.00000,0.00000 $$SPICE_EPILOG_PRIORITY 5 000002 0.00000,0.00000 Package package name for PCB layout 000001 0.00000,0.00000 GND U? GND 1 $$SPICE_PROLOG_PRIORITY 5 000002 0.00000,0.00000 $$SPICE_EPILOG_PRIORITY 5 000002 0.00000,0.00000 Package package name for PCB layout 000001 0.00000,0.00000 SST39LF010 U? SST39LF010 1 $$SPICE_PROLOG_PRIORITY 5 000002 0.00000,0.00000 $$SPICE_EPILOG_PRIORITY 5 000002 0.00000,0.00000 Package package name for PCB layout 000001 0.00000,0.00000 SST39LF010 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 D0 D1 D2 D3 D4 D5 D6 A10 A11 A12 A13 A14 A15 A16 /CE /OE /WE D7 Female Header 34 Pin U? Female Header 34 Pin 1 $$SPICE_PROLOG_PRIORITY 5 000002 0.00000,0.00000 $$SPICE_EPILOG_PRIORITY 5 000002 0.00000,0.00000 Package package name for PCB layout 000001 0.00000,0.00000 A0 A1 A2 A3 A4 A5 A6 A7 A8 D0 D1 D2 D3 D4 D5 D6 D7 GP0 GP1 GP2 GP3 GP4 Vdd Vss V+ /RST /OE /INT /BUSY R/W /CE SCK GP5 A9 IDT71V30S/L U? IDT71V30S/L 1 $$SPICE_PROLOG_PRIORITY 5 000002 0.00000,0.00000 $$SPICE_EPILOG_PRIORITY 5 000002 0.00000,0.00000 Package package name for PCB layout 000001 0.00000,0.00000 IDT71V30S/L A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R IO0R IO1R IO2R IO3R IO4R IO5R IO6R IO7R /OER /INTR /BUSYR R/WR /CER /OEL /INTL /BUSYL R/WL /CEL A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L IO0L IO1L IO2L IO3L IO4L IO5L IO6L IO7L 0 0 FF0000 0000FF 000000 000000 208000 000000 4040C0 208020 FFFFFF AFFFFF FF0000 FF0000 MainBrain32 - Memory Larry Knight 0.1 μF 0.1 μF Vdd Vdd