//**********************************************************// 
//              MainBrain32.h                               //
//                                                          //
//                                                          //
//                                                          //
//**********************************************************//
const unsigned char courier_new_16pt_bold[0];
const unsigned char splash_logo[0];
const uint16_t lut[0];
const unsigned char SYSTEM_STRING[0];
const uint16_t SYSTEM_STRING_OFFSET[0];

extern const unsigned int PRI_FREQ;
extern const unsigned int SEC_FREQ;
extern const unsigned int RAM_SIZE;

unsigned char d4, d3, d2, d1, d0;

unsigned long nib0, nib1, nib2, nib3, nib4, nib5, nib6, nib7, nib8, nib9;
unsigned long working_reg;
unsigned long ext_reg;
unsigned long main_reg;
unsigned long extra_reg;
unsigned long ROM_data_lo;
unsigned long ROM_data_hi;

unsigned short int data_x;
unsigned short int data_y;
unsigned short int data_i;
unsigned short int n;

unsigned int d_hex[7];
unsigned int i_hex;
unsigned int flash_size;
unsigned int delay_us;
unsigned int DQ0;
unsigned int DS18B20_LSW;
unsigned int DS18B20_MSW;
unsigned int bcd32;

int mdata_71v30;
uint8_t data_39LF010;
int erase_sector;
int Display_Read;
int pixel_color;
int wr_pixels;
int fore_color;
int col_count;
int back_color;
int string_index;
int col_end;
int col_start;
int row_start;
int row_end;
int back_level;
int ascii_char;
int SPI3Data;
int total_pixels;
int sysclk_freq;
int pbclk_freq;
int rect_color;
int address_71v30;
int address_39LF010;
int col;
int peak_I;
int lowest_I;
int Flash_MID;
int Flash_DID;
int sram_test;
int sram_i;
int sram_j;
int ch;
int scrn_tmr;
int test;
int temp_data;
int DS18B20_status;
int RX_Data[100];
int UART_Count;
int vchar;
int hchar;
int adc_x[5];
int p;
int adc_y[5];
int q;
int sram_test_data[1024];
int i;
int ii;
int debounce;